The field of the present invention is electronic circuits for frequency synthesis. More particularly, the present invention relates to a prescaler electronic circuit for use with a fractional-N synthesizer.
Wireless communication systems transmit and receive modulated radio frequency (RF) signals, generally in accord with one or more telecommunications standards. These telecommunication standards, such as GSM, CDMA, CDMA2000, PDC, PHS, and others, generally set out specific and narrow bands of frequency operation. In order to maintain compliance with the frequency standards, wireless transceivers may use a crystal controlled oscillator to provide a highly accurate and stable frequency source, which controls and maintains the frequency output of a higher frequency local oscillator, such as a voltage controlled oscillator (VCO). In operation, the wireless transceiver may often need to change channels or modes, and therefore the modulation frequency generated by the VCO.
The high frequency VCO generates a high frequency signal at the desired modulation frequency, which is defined in the implemented telecommunication standard. The modulation signal may be, for example, several hundred Megahertz, with some telecommunication standards now operating in the Gigahertz frequencies. Although the VCO generates high frequency signals, the VCO is a relatively unstable frequency source, and is subject, for example, to frequency drift and accuracy errors. In order to increase the accuracy and stability of the VCO, the VCO uses the crystal controlled oscillator as a frequency reference. To do so, a prescaler circuit may be used to divide the VCO signal to a desired lower frequency. A controller in the wireless device determines the desired ratio between the reference oscillator and the VCO, and generates an appropriate divide ratio. Using the selected divide ratio, the local VCO signal is divided to a lower frequency, which is then locked to the reference signal from the crystal controlled oscillator, often by using a standard phase locked loop (PLL) circuit. If there is a difference in frequency between the reference signal and the divided signal, then a feedback loop is used to appropriately adjust the frequency of the VCO. In this way, the VCO frequency is adjusted according to the divide ratio used in the prescaler. In another use, the divide ratio of the prescaler may be changed to generate different signal frequencies. In this way, different lower frequency signals may be readily available for use.
A prescaler typically has two available divide ratios and has an input control line that allows a control circuit to set a first mode where the prescaler divides by a first divide ratio, or set a second mode where the prescaler divides by a second divide ratio. Since the prescaler has at least some components that operate at the frequency of the local oscillator signal, the prescaler circuit needs to be implemented with minimal components, and with structures selected to accommodate timing and power needs. As oscillator frequencies increase, and the demands for stable and accurate frequency sources increase, there are more demands being placed on prescalers.
A typical known prescaler is arranged to divide either at an N factor or at an (N+1) factor. Such a prescaler is often referred to as an N/(N+1) prescaler. Common prescaler values are 4/5; 8/9; and 16/17. In using a prescaler, a control circuit instructs the prescaler to divide an input frequency by a particular divide ratio. The magnitude and range of the required divide ratios are determined according to the frequency of the reference oscillator, the frequency of the VCO, and the requirements of the communication standard that is to be implemented. More particularly, the required communication standard is likely to define specific frequency bands and channel separations that a radio device must use. In practice, it is usual to define the divide ratios according to the minimum channel spacing required by the communication standard. In order to efficiently implement the radio, and to fully use the available frequency spectrum, the divide ratios are almost always contiguous. That is, the prescaler is able to implement every divide ratio at or above a given minimum divide ratio. For example, an 8/9 prescaler is able to implement divide ratios contiguously from a minimum divide ratio of 56. For example, the 8/9 prescaler can divide by 56, 57, 58, 59, and every integer value thereafter. Although the 8/9 prescaler may implement some divide ratios less than 56, it cannot do so contiguously. For example, the 8/9 prescaler cannot practically implement a divide ratio of 55. In a similar manner, the 4/5 prescaler is contiguous from a minimum divide ratio of 12, and the 16/17 prescaler is contiguous from a minimum divide ratio of 240.
To reduce power consumption and space requirements, known prescalers are designed to conserve components, power, and space. Over the years, standard designs have evolved which more efficiently use logic components. For example, the 4/5 prescaler can be implemented using 3 flip-flops and associated logic gates, the 8/9 prescaler can now be implemented using 4 flip-flops and associated logic gates, and the 16/17 prescaler can now be implemented using 5 flip-flops and associated logic gates. Further, it is important to consider how much circuitry must operate at the frequency of the VCO, since the timing requirements for these components tend to be critical, as well as having increased power needs. In known designs, several of the flip-flops typically operate at the VCO frequency. For example, in the 8/9 prescaler, which has a total of 4 flip-flops, 3 of those flip-flops operate at full VCO frequency.
In another consideration, prescalers are designed to implement particularly efficient division algorithms. For example, N is almost always selected to be a power of 2, since this allows a simple bit shift to implement a divide-by-2 function. Other implementations would become unnecessarily complex. However, the selection of simplified electronic arrangements limits the flexibility of the division algorithm. Take for example the division algorithm for a known 8/9 prescaler. Any natural number may be written as D=M*8+A, where M and A are natural, and A is in the range of 0 and 7. As understood by one skilled in the art, a natural number is an integer which is positive or zero. However, implementing a practical 8/9 prescaler usually involves a more restrictive algorithm, which may be written as D=(M−A)*8+A*9. This algorithm is the division process as actually implemented in the electronic components, and illustrates some of the limitations inherent in the 8/9 prescaler. For example, the electronic components are only able to act on natural numbers, and since A has a maximum value of 7, then M must have a minimum value of 7. Otherwise, the term (M−A) results in a negative number. Using this implementation, the minimum value of D is 56 (M=7 and A=0).
Therefore, there exists a need for a frequency prescaler that provides adequate frequency reduction, required frequency resolution, and that can be efficiently and robustly implemented.